question about low-level SMP detail;s in G4 Macs?

[darthnvader]

http://bitsavers.computerhistory.org/pd ... rp1_7a.pdf

I believe the dual cpu G4 had mac model powermac3,3 instead of powermac3,1

Best,
Cat_7

I got confused and over excited, anyway, I now need to allow access to 0x17 and 0x18 of the GPIO because linux smp kick is hitting these two register of the GPIO....

[darthnvader]

http://bitsavers.computerhistory.org/pd ... rp1_7a.pdf

I believe the dual cpu G4 had mac model powermac3,3 instead of powermac3,1

Best,
Cat_7

The patches for the smp for qemu are now in the master!

Somebody made some changes, but we are still in a hanging state, they added access to GPIO register 0x4 and 0xc, but I'm not sure we can kick the second CPU yet, so.........

IDE still seems to be stuck with SMP, I think because they mask CPU resets behind the IDE bus, or a patch was applied that is broken or needs a patch to Openbios we don't have yet....

Mate 16.04 Live CD no longer reports Processor is stuck, but we still can't get the root device to verify isn't running either, and we now have no input either....

Code: Select all

./qemu-system-ppc64-unsigned -M mac99,via=pmu -m 256 -smp 4 --accel tcg,thread=multi  -bios /Users/jam/OBPure/openbios/obj-ppc/openbios-qemu.elf -cpu 7450 -cdrom /Users/jam/Downloads/ubuntu-mate-14.04.1-dev.34508-desktop-powerpc.iso --nographic
s>> et_property: NULL phandle

>> =============================================================
>> OpenBIOS 1.1 [Feb 16 2025 17:30]
>> Configuration device id QEMU version 1 machine id 1
>> CPUs: 4
>> Memory: 256M
>> UUID: 00000000-0000-0000-0000-000000000000
>> CPU type PowerPC,G4
>> CPU type PowerPC,G4
>> CPU type PowerPC,G4
>> CPU type PowerPC,G4
milliseconds isn't unique.
Welcome to OpenBIOS v1.1 built on Feb 16 2025 17:30
Trying hd:,\\:tbxi...
Trying hd:,\ppc\bootinfo.txt...
Trying hd:,%BOOT...
No valid state has been set by load or init-program

0 > boot cd:,\\:tbxi >> switching to new context:

call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf
call-method color!: exception -21 
>> call-method color! failed with error ffffffdf

Config file read, 2690 bytes

Welcome to Ubuntu MATE 14.04 LTS (Trusty Tahr)!

This is an Ubuntu MATE live CDROM,
built on 20141211.

The default option is 'live'.

The plain options are for the PowerPC family of
processors (from 601 to G4). The *64 options are for
64bit PowerPC processors, which include the IBM
Power3, Power4, Power5, ... boxes, as well as the
Apple G5 boxes. 

Press the tab key for a list of options, or type
'help' for help.

Further information can be found in the community
maintained "PowerPC FAQ" and "PowerPC Known Issues"
wiki pages:

wiki.ubuntu.com/PowerPCFAQ
wiki.ubuntu.com/PowerPCKnownIssues
Welcome to yaboot version 1.3.16
Enter "help" to get some basic usage information

WARNING: Bootstrap partition type is wrong: "Apple_HFS"
         type should be: "Apple_Bootstrap"

boot: live
Please wait, loading kernel...
   Elf32 kernel loaded...
Loading ramdisk...
ramdisk loaded at 01a00000, size: 18324 Kbytes
OF stdout device is: /pci@f2000000/mac-io@c/escc@13000/ch-a@13020
Preparing to boot Linux version 3.13.0-40-powerpc-smp (buildd@sagari) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #69-Ubuntu SMP Thu Nov 13 17:56:07 UTC 2014 (Ubuntu 3.13.0-40.69-powerpc-smp 3.13.11.10)
Detected machine type: 00000400
command line: 
memory layout at init:
  memory_limit : 00000000 (16 MB aligned)
  alloc_bottom : 02be6000
  alloc_top    : 10000000
  alloc_top_hi : 10000000
  rmo_top      : 10000000
  ram_top      : 10000000
found display   : /pci@f2000000/QEMU,VGA@e, opening... done
copying OF device tree...
Building dt strings...
Building dt structure...
Device tree strings 0x02ce7000 -> 0x02ce75dd
Device tree struct  0x02ce8000 -> 0x02cf0000
Calling quiesce...
returning from prom_init
Hello World !
setup_arch: bootmem
arch: exit
smp_core99_probe
smp_core99_kick_cpu
smp_core99_kick_cpu done
smp_core99_kick_cpu
smp_core99_kick_cpu done
smp_core99_kick_cpu
smp_core99_kick_cpu done
             
Unable to find a med

[darthnvader]

We’ve got a race condition I’m working on nailing down, my have something to do with open bios not assigning interrupts or the interrupt-parent to additional CPUs.

I can’t see an interrupt property for CPU0, so I’m not sure if open bios assigns an interrupt or QEMU does or neither for one CPU?

[adespoton]

We’ve got a race condition I’m working on nailing down, my have something to do with open bios not assigning interrupts or the interrupt-parent to additional CPUs.

I can’t see an interrupt property for CPU0, so I’m not sure if open bios assigns an interrupt or QEMU does or neither for one CPU?

Hmm... how's it done on a real SMP G4 Mac?

This thread might be useful: https://forums.macrumors.com/threads/po ... 653/page-2 -- it's for G5 support, but still deals with OpenBIOS and SMP handling.

[darthnvader]

We’ve got a race condition I’m working on nailing down, my have something to do with open bios not assigning interrupts or the interrupt-parent to additional CPUs.

I can’t see an interrupt property for CPU0, so I’m not sure if open bios assigns an interrupt or QEMU does or neither for one CPU?

Core 1 works, it can compute, if I set it in state 1 rather than state zero, it handles the IRQ storm rather than CPU 0.

By handle the IRQ storm I mean Core 1 does the IRQ handling but it doesn't fix the race condition.

We're going to have to set these CPUs up proper in Openbios........

[Cat_7]

Just a small update:

Thanks to Zoltan, we've now got some support for multi-processor running in qemu-system-ppc64. It is not perfect in that it is only relatively stable in Mac OS X 10.3 to 10.5. Mac OS 9.x freeze after some seconds. However, initial benchmarks show a ~50% performance increase.

Zoltan's other qemu projects: http://qmiga.codeberg.page/

Best,
Cat_7

[darthnvader]

If 2 is good, 4 is better!

[adespoton]

Wow, that's great! How long until this gets into one of the unified experimental builds (multiple displays, screamer, etc.)?

[darthnvader]

Wow, that's great! How long until this gets into one of the unified experimental builds (multiple displays, screamer, etc.)?

Hopefully Cat7 can work us up an experimental build with SMP.

For now OS 9 is a no go for SMP, but I'm still working on it and have some idea what is casing the system freeze when apps use the 2nd CPU.

10.0 untested.

10.1 untested

10.2 untested

10.3 untested.

10.4.x works great with 2 or 4 CPUs Classic mode can use all 4 cores.

10.5 Doesn't support more than 2 G4's, could be fixed with a custom kernel but it's way down on my list.

10.6 DP PPC Works with 2 cores, could be fixed with a custom kernel but it's way down on my list.

Tiger is my Target, as that's the OS I use because I can run classic and still have a pretty rich and compatible OS X.

Others are welcome to test and report bugs and I may or may not look into them, or they can learn the code and bug fix and extend features.

[adespoton]

SMP should work with 2 CPUs as far back as 10.2; before that, I have no idea.

I saw your comments regarding OS 9 and the 2nd CPU issues; could it be something to do with the different ways that OF is managing the hardware between OS 9 and OS X? Something OS 9 isn't checking? If so, could we just write a little Forth routine to implement whatever OS X is doing directly in OF so that OS 9 doesn't lose context?

Or have you moved past that now and it's just going to take some work to implement what's needed?

[darthnvader]

SMP should work with 2 CPUs as far back as 10.2; before that, I have no idea.

I saw your comments regarding OS 9 and the 2nd CPU issues; could it be something to do with the different ways that OF is managing the hardware between OS 9 and OS X? Something OS 9 isn't checking? If so, could we just write a little Forth routine to implement whatever OS X is doing directly in OF so that OS 9 doesn't lose context?

Or have you moved past that now and it's just going to take some work to implement what's needed?

OS 9 and Linux seem sensitive to the timebase sync( timebase-enable ) We don't have that implemented correct in smp code in Qemu-ppc, but I got the keylargo white paper so maybe in a few days I can come up with some working code for OS 9 and Linux, but Tiger seems to use a software OS based timebase sync as does Leopard and Snow Leopard.

Andrew said Jaguar had issues with SMP, but I've not tested.

[darthnvader]

SMP should work with 2 CPUs as far back as 10.2; before that, I have no idea.

I saw your comments regarding OS 9 and the 2nd CPU issues; could it be something to do with the different ways that OF is managing the hardware between OS 9 and OS X? Something OS 9 isn't checking? If so, could we just write a little Forth routine to implement whatever OS X is doing directly in OF so that OS 9 doesn't lose context?

Or have you moved past that now and it's just going to take some work to implement what's needed?

OS 9 and Linux seem sensitive to the timebase sync( timebase-enable ) We don't have that implemented correct in smp code in Qemu-ppc, but I got the keylargo white paper so maybe in a few days I can come up with some working code for OS 9 and Linux, but Tiger seems to use a software OS based timebase sync as does Leopard and Snow Leopard.

Andrew said Jaguar had issues with SMP, but I've not tested.

Even with the Keylargo white paper I can't figure this out, OS 9 still freezes even after over 8 hours of trying to enable timebase sync, so that's all I can do:

macio_set_gpio setting GPIO 27 to 1
Forcing TBEN (GPIO 27) to 1 (reg value: 0x2)
ppc_tb_start_all() called: Timebase resumed. Frozen value was 0
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 4 to 1
macio_gpio_irq_deassert deasserting GPIO 4
macio_set_gpio setting GPIO 5 to 1
macio_gpio_irq_deassert deasserting GPIO 5
macio_set_gpio setting GPIO 6 to 1
macio_gpio_irq_deassert deasserting GPIO 6
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 0
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_gpio_write addr 0x24 val 0x3c
macio_set_gpio setting GPIO 28 to 0
macio_gpio_read addr 0x4 val 0x2
macio_gpio_write addr 0xc val 0x6
macio_set_gpio setting GPIO 4 to 0
macio_gpio_irq_assert asserting GPIO 4
macio_set_gpio setting GPIO 4 to 0
macio_gpio_read addr 0x4 val 0x0
macio_gpio_read addr 0x4 val 0x0
macio_gpio_write addr 0xc val 0x0
macio_set_gpio setting GPIO 4 to 1
macio_gpio_irq_deassert deasserting GPIO 4
macio_set_gpio setting GPIO 4 to 1
macio_gpio_read addr 0x1b val 0x2
macio_gpio_write addr 0x23 val 0x2
macio_set_gpio setting GPIO 27 to 1
Forcing TBEN (GPIO 27) to 1 (reg value: 0x2)
ppc_tb_start_all() called: Timebase resumed. Frozen value was 0
macio_gpio_read addr 0x1b val 0x2
macio_gpio_write addr 0x23 val 0x6
macio_set_gpio setting GPIO 27 to 0
Forcing TBEN (GPIO 27) to 1 (reg value: 0x2)
ppc_tb_start_all() called: Timebase resumed. Frozen value was 0
macio_gpio_read addr 0x1b val 0x4
macio_gpio_write addr 0x23 val 0x0
macio_set_gpio setting GPIO 27 to 0
Forcing TBEN (GPIO 27) to 1 (reg value: 0x6)
ppc_tb_start_all() called: Timebase resumed. Frozen value was 0
macio_gpio_write addr 0x24 val 0x3c
macio_set_gpio setting GPIO 28 to 0
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_gpio_write addr 0x2a val 0x4
macio_set_gpio setting GPIO 34 to 0
macio_gpio_write addr 0x2a val 0x5
macio_set_gpio setting GPIO 34 to 1
macio_gpio_write addr 0x2a val 0x0
macio_set_gpio setting GPIO 34 to 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_gpio_write addr 0x2a val 0x4
macio_set_gpio setting GPIO 34 to 0
macio_gpio_write addr 0x2a val 0x5
macio_set_gpio setting GPIO 34 to 1
macio_gpio_write addr 0x2a val 0x0
macio_set_gpio setting GPIO 34 to 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1
macio_set_gpio setting GPIO 1 to 0
macio_gpio_irq_assert asserting GPIO 1
macio_set_gpio setting GPIO 1 to 1
macio_gpio_irq_deassert deasserting GPIO 1